1. Field of the Invention
The present invention relates to the fabrication of semiconductor integrated circuit structures and, in particular, to a method of simultaneously forming salicide and local interconnects in MOS technologies.
2. Discussion of the Related Art
U.S. Pat. No. 5,010,032, issued Apr. 23, 1991, discloses a process for making CMOS devices that include retractery metal nitride interconnect layers. In particular, the '032 patent discloses a process flow in which titanium is deposited on the source/drain regions and adjacent oxide and then heated in a nitrogen-bearing atmosphere by rapid thermal processing (RTP) to form TiN on the oxide and a stacked TiN/TiSi.sub.2 layer on the source/drain regions.
The process of the '032 patent can result in formation of non-uniform silicide due to oxide guttering, i.e. attraction of oxide into the silicide during silicide formation. Nitrogen can also diffuse into the titanium during the RTP step with deleterious effects.
U.S. Pat. No. 5,567,651, issued Oct. 22, 1996, discloses a process for forming cobalt silicide on the source/drain regions and polysilicon gate areas of an MOS device. A titanium nitride film is deposited on a cobalt film following the patterning of the polysilicon gate, source/drain implant and sidewall spacer formation. Following rapid thermal processing, which converts the cobalt to CoSi, a selective etch is performed to remove the TiN layer and unreacted cobalt. A second heat treatment is then performed to convert the CoSi to the low-resistivity CoSi.sub.2 phase.